A chip carrier, also known as a chip container or chip package, is the container microchips (integrated circuits) come in, which is then plugged into or soldered onto its respective circuit board, such as a CPU being plugged into a motherboard. Many modern examples use surface-mount technology and are designed to be installed by machines, with tolerances too small for convenient manipulation by humans.
Examples:
* CPGA (Ceramic Pin Grid Array)
* Dual in-line package
* OPGA (Organic Pin Grid Array)
* Flip-chip pin grid array
* Pin grid array
In microelectronics, a dual in-line package (DIP), sometimes called a DIL package, is an electronic device package with a rectangular housing and two parallel rows of electrical connecting pins, usually protruding from the longer sides of the package and bent downward. A DIP is usually referred to as a DIPn, where n is the total number of pins. For example, a microcircuit package with two rows of seven vertical leads would be a DIP14.
DIPs may be used for integrated circuits (ICs, "chips"), like microprocessors, or for arrays of discrete components such as resistors or toggle switches. They can be mounted on a printed circuit board (PCB) either directly using through-hole technology, or using inexpensive sockets to allow for easy replacement of the device and to reduce the risk of overheat damage during soldering.
Pin spacing
The most common DIPs have an inter-lead spacing (lead pitch) of 0.1" (2.54 mm) and a row spacing of either 0.3 in (7.62 mm) or 0.6 in (15.24 mm). Typical pin counts are 8 or any even number from 14 to 24 (less common 28) for 0.3 in packages, and 24, 28, 32 or 40 (less common 36, 48 or 52) for 0.6 in packages. Where there is a need to differentiate between the two widths for the same pin count the term "Skinny DIP" is used to refer to the 0.3 in version. JEDEC-standards also specify less common packages with a row spacing of 0.4 in (10.16 mm), or 0.9 in (22.86 mm) with a pin-count of up to 64. Other standardized variants include a lead pitch of 0.07 in (1.778 mm) at a row spacing of 0.3 in, 0.6 in or 0.75 in. The former Soviet Union and Eastern bloc countries used similar packages, but with a metric inter-lead spacing of 2.5 mm, rather than 2.54 mm (or 0.1 in).
Several DIP variants exist, mostly distinguished by packaging material:
* Ceramic Dual In-line Package (CERDIP)
* Plastic Dual In-line Package (PDIP)
* Shrink Plastic Dual In-line Package (SPDIP) – A shrink version of the PDIP with a 0.07 in (1.778 mm) lead pitch
DIPs were the mainstream of the microelectronics industry in the 1970s and 80s. Their use has subsided in recent years due to the emerging new surface-mount technology (SMT) packages such as PLCC and SOIC.
For programmable devices like EPROMs and GALs, DIPs remained popular for many years due to their easy handling with external programming circuitry. However, with In-System Programming (ISP) technology now state of the art, this advantage of DIPs is rapidly losing importance as well. Through the 1990's, devices with pin counts below 20 were manufactured in a DIP format in addition to the newer formats. Since about 2000, newer devices are often unavailable in the DIP format.
Orientation and pin numbering
DIPs have an orientation notch in one end. If the chip is held so that the long axis is horizontal and the notch is at the left end, pin #1 is the leftmost pin in the bottom row. Pins are numbered counter-clockwise from there, i.e. left to right across the bottom row, then right to left across the top row. This allows automated chip-insertion machinery to ensure correct orientation of the chip by mechanical sensing.
pin grid array (FC-PGA or FCPGA) is a form of pin grid array processor architecture package in which the die faces downwards on the top of the CPU with the back of the die exposed. This allows the die to have a more direct contact with the heatsink or other cooling mechanism.
The FC-PGA package is used on certain Intel Celeron, Pentium III, and Pentium 4 family microprocessors. FC-PGA processors fit into zero insertion force (ZIF) Socket 370 and Socket 478 motherboard sockets; similar packages have also been used by AMD.
FC-PGA packaging is used by Pentium III processors, and Celeron 533, unofficially called 533A, processors onward. Earlier Celeron processors used PPGA packaging, the fastest was at 533 MHz.
FC-PGA2, adds a heat spreader over the silicon core and is used on late Pentium III processors and most Pentium 4 and Celeron processors using Socket 478 (180nm Willamette and 130nm Northwood). FC-PGA4 is used by Intel Pentium 4 and Celeron D processors using 90 nm process (Prescott based) also with integrated heat spreader. Intel Mobile Pentium 4-M processors did not have the integrated heat spreader and so use FC-PGA packaging.
Intel replaced FC-PGA style packaging with the land grid array (LGA775) or FC-LGA4 packaging on Prescott-based Pentium 4 and Celeron D processors which no longer have pins.
Celeron processors are also available in Slot 1 SEPP. Pentium III processors are also available in Slot 1 Single Edge Contact Cartridge 2 packaging. Pentium 4 processors are also available in Socket 423 Organic Land Grid Array (OLGA) on Interposer (OOI) (INT2 and INT3) and Socket T LGA775 packaging.
Adapters are available to allow a PPGA Celeron or FC-PGA Celeron's and Pentium III's to plug into a Slot 1 connector.
The micro-FCPGA (flip-chip plastic grid array) package consists of a die placed face-down on an organic substrate. An epoxy material surrounds the die, forming a smooth, relatively clear fillet. The package uses 478 pins, which are 2.03 mm long and .32 mm in diameter. While there are several micro-FCPGA socket designs available, all of them are designed to allow zero-insertion force removal and insertion of the processor. Different from micro-PGA, the micro-FCPGA does not have an interposer and it includes capacitors on the bottom side.
This page is from http://en.wikipedia.org/wiki/Chip_carriers All text is available under the terms of the GNU Free Documentation License (http://en.wikipedia.org/wiki/Wikipedia:Copyrights)
